12864的verilog程序.doc

module newlcd(clk,rst,lcd_e,lcd_rs,lcd_rw,data,lcd_psb); input clk; input rst; //input lcd_ret; output lcd_psb; output lcd_e; output lcd_rs; output lcd_rw; output [7:0] data; reg lcd_e; reg lcd_rw; reg lcd_rs; reg [7:0] data; reg [21:0] clkcnt; reg clkdiv; reg double_div; reg flag; reg [7:0] state; wire bz_clkcnt; wire lcd_psb; parameter idle=8b0000_0000; parameter setfunction=8b0010_0000; parameter switchmode=8b0000_1000; parameter setmode=8b0000_0100; parameter clear=8b0000_0001; parameter setddram=8b1000_0000; parameter write1=8b1111_0000; parameter write2=8b1110_0000; assign lcd_psb=1b1; assign bz_clkcnt=(clkcnt[21]==1)?1:0; always@(posedge clk or negedge rst) begin if(rst==0) clkcnt=0; else if(clkcnt[21]==1) clkcnt=0; else clkcnt=clkcnt+1; end always@(posedge bz_clkcnt or negedge rst) begin if(rst==0) clkdiv=0; else clkdiv=~clkdiv; end always@(posedge clkdiv) begin if(rst==0) double_div=0; else double_div=~double_div; end always@(negedge clkdiv) begin if(rst==0) lcd_e=0; else lcd_e=~lcd_e; end always@(posedge double_div or negedge rst) begin if(rst==0) begin flag=0; state=0; end else begin case(state) idle: begin if(flag==0) begin flag=1; state=setfunction; end else begin rw=1; end end setfunction: begin lcd_rw=0; lcd_rs=0; data=8h30; state=switchmode; end switchmode: begin lcd_rw=0; lcd_rs=0; data=8h0c; state=clear; end clear: begin lcd_rw=0; lcd_rs=0; data=8h01; state=setmode; end setmode: begin lcd_rw=0; lcd_rs=0; data=8h06; state=setddram; end setddram: begin lcd_rw=0; lcd_rs=0; data=8h80; state=write1; end write1: begin lcd_rw=0; lcd_rs=1; data=a; state=idle; end end