nvidia设计验证笔试题（Clock笔试）.docVIP

NVIDIA 2016 Campus RecruitmentExam Test Paper SH-ASIC-DV Cover Page Total pages: 10 Exam Duration: 90 minutes * Please answer all the questions in English Applied Position: ASIC Design/Verification Engineer（Clock） Candidate Chinese Full Name/中文名 Candidate School Name/毕业学校 Candidate Contact Number/手机号码 Candidate E-mail address/邮箱地址 Current Degree/学历 Master Graduation Time/毕业时间 / 1 (Year/ Month) Major/专业The two questions below are used only for reference, they are not criteria for hiring. Please fill in accurately. (以下两问题仅作为参考信息，不作为新员工录用标准, 请如实填写) Availability for Internship before graduation/毕业前能否作实习生(Yes/No) ?When will be available for internship/何时可以开始实习 ? Total Points ( 80 ) Please fill Interviewee column to rate yourself on below items from 1~5 before you start the written test: 2 - below average 3 - on average 4 - good 5 - excellent Items Interviewee Interviewer A Interviewer B Basic Logic Design(combinational logic/sequential logic) excellent Basic scripting language(Perl or Python, or …) good C/C++ programming good Problem Solving excellent Communication Skills (express clearly, explain logically) excellent Note: Read questions carefully and answer as much as you can. There are scratch papers provided, if you don’t have them, please speak out. You can select English or Chinese to answer questions Question1 (10 points): Design the schematic for the logic of new_en = eco_en ? eco_mask en : en; (Please ONLY use NOR2 cells, only “eco_en”, “en” and “eco_mask” are the inputs to your logic, and try to use as less cells as possible) Question 2 (10 points): ? #1: What is setup timing and hold timing? You can draw diagram or waveform to explain. #2: What is clock jitter and its impact to timing? Question 3 (10 points): Draw design diagram or state machine for following sequence detection logic: if input sequence of “0110” shows up, output 1’b1; otherwise, outputs 1’b0. Please list how many re