VHDL双语教学第3章.pptVIP

VHDL Synthesis Simulation (Basic Language Items) Agenda Overview Entity Architecture Library Use Package Configuration Basic Language Framework library ieee; use ieee.std_logic_1164.all; --------------------------------------------- entity XYZ is port ( A, B, C : in std_logic; -- Comments F : out std_logic ); end XYZ; --------------------------------------------- architecture XYZ_arch of XYZ is begin ? F = (A and B) or (B and C) or (C and A); ? end XYZ_arch; Agenda Overview Entity Keywords Port Generic Architecture Library Use Package Configuration Entity library ieee; use ieee.std_logic_1164.all; --------------------------------------------- entity XYZ is port ( A, B, C : in std_logic; F : out std_logic ); end XYZ; --------------------------------------------- architecture XYZ_arch of XYZ is begin F = (A and B) or (B and C) or (C and A); end XYZ_arch; Entity Definition entity entity_name is [Generics;] [Ports;] [Other Declarative Parts;] [Statements;] end [ entity ] [ entity_name ] ; Entity Examples (ROM) entity ROM is port ( D0 : out bit; D1 : out bit; D2 : out bit; D3 : out bit; D4, D5, D6, D7 : out bit; A : in bit_vector(7 down to 0) ); end ROM; Entity Examples (Adder) entity Full_Adder is port (X, Y, Cin: in Bit; Cout, Sum: out Bit) ; end entity Full_Adder ; Entity Examples (n-input AND) entity ANDN is generic (wid : integer := 2); port ( X : in bit_vector(wid-1 downto 0); F : out bit ); end; Entity Example (Empty Entity) entity Test_Bench is end entity Test_Bench ; Agenda Overview Entity Keywords Port Generic Architecture Library Use Package Configuration Entity Definition (Ports) Port Example (AND