74LS138英文资料.docVIP

54LS138/DM54LS138/DM74LS138, 54LS139/DM54LS139/DM74LS139 Decoders/Demultiplexers General Description  June 1989 These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing appli- cations, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay intro- duced by the decoder is negligible. The LS138 decodes one-of-eight lines, based upon the con- ditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when ex- panding. A 24-line decoder can be implemented with no ex- ternal inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The LS139 comprises two separate two-line-to-four-line de- coders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. All of these decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its driving circuit. All inputs are clamped with high-performance Connection Diagrams Dual-in-Line Package TL/F/6391 – 1 Order Number 54LS138DMQB, 54LS138FMQB, 54LS138LMQB, DM54LS138J, DM54LS138W, DM74LS138M or DM74LS138N See NS Package Number E20A, J16A, M16A, N16E or W16A Schottky diodes to suppress line-ringing and simplify system design. Features Y Designed specifically for high speed: Memory decoders Data transmission systems Y LS138 3-to-8-line decoders incorporates 3 enable in- puts to simplify cascading and/or data reception Y LS139 contains two fully independent 2-to-4-line decod- ers/demultiplexers Y Schottky clamped for high performance Y Typical propag