基于quartus2十六进制8位数码管扫描显示频率计设计.docVIP

Ftctrl时钟控制模块的vhdl代码： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FTCTRL IS PORT (CLKK : IN STD_LOGIC; CNT_EN : OUT STD_LOGIC; RST_CNT: OUT STD_LOGIC; Load : OUT STD_LOGIC); END FTCTRL; ARCHITECTURE behav OF FTCTRL IS SIGNAL Div2CLK : STD_LOGIC; BEGIN PROCESS ( CLKK ) BEGIN IF CLKKEVENT AND CLKK = 1 THEN Div2CLK = NOT Div2CLK; END IF; END PROCESS; PROCESS (CLKK ,Div2CLK) BEGIN IF CLKK=0 AND Div2CLK=0 THEN RST_CNT=1; ELSE RST_CNT =0; END IF; END PROCESS; Load = NOT Div2CLK; CNT_EN =Div2CLK; END behav; 4位计数器cnt4b的vhdl代码： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT4B IS PORT (Fin,CLR,ENABL: IN STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT : OUT STD_LOGIC ); END CNT4B; ARCHITECTURE behav OF CNT4B IS BEGIN PROCESS(Fin,CLR,ENABL) VARIABLE Q : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF CLR=1 THEN Q := (OTHERS=0); ELSIF FinEVENT AND Fin=1 THEN IF ENABL=1 THEN IF Q15 THEN Q :=Q+1; ELSE Q := (OTHERS=0); END IF; END IF; END IF; IF Q=1111 THEN COUT=1; ELSE COUT=0; END IF; DOUT = Q; END PROCESS; END behav; 分频器模块fp的vhdl代码： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY fp IS PORT( inclk : IN STD_LOGIC; outclk : OUT STD_LOGIC); END fp; ARCHITECTURE a OF fp IS SIGNAL fp : STD_LOGIC_VECTOR(3 downto 0); SIGNAL f : STD_LOGIC; BEGIN PROCESS(inclk) BEGIN IF inclkevent and inclk=0 THEN IF fp=4 then fp=0000; f=not f; ELSE fp=fp+1; END IF; END IF; END PROCESS; outclk=f; END a; --------------------------------------------------------------------------------------------------------------------------------- 缓存加数码管位选地址信号输出模块topreg32b的vhdl代码： LIBRARY IEEE; USE IEEE.STD_LOGI