VHDL与数字电路设计PPT课件-第七章 状态机设计.pptVIP

VHDL与数字电路设计 本章内容 状态机的电路设计 交通灯控制器设计 1、状态机的电路设计 我们可以用输入信号X和电路状态Q来描述时序电路的逻辑功能，这时时序电路称为状态机（State Machine）。 根据输出信号和输入信号以及电路状态的关系，状态机可以分为两种：穆尔（Moore）型和米利（Mealy）型。 Y=F[X,Q] Y=F[Q] 米利（Mealy）型： 穆尔（Moore）型： （1） More型状态机 S0 S2 0/0 1/0 S3 1/0 S1 1/1 0/0 0/1 0/0 1/0 输入信号影响状态的转换。 输出信号和输入信号无关。 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY more IS PORT( Clk,reset: in Std_logic; din: in Std_logic; op: out Std_logic); END more; ARCHITECTURE a OF more IS TYPE STATE_TYPE IS (s0, s1, s2,s3); SIGNAL state: STATE_TYPE; BEGIN S0 S2 0/0 1/0 S3 1/0 S1 1/1 0/0 0/1 0/0 1/0 PROCESS (clk,reset) BEGIN If reset = 1 THEN state = s0; else IF clkEvent AND clk = 1 THEN CASE state IS WHEN s0 = IF din=1 THEN state = s1; else state=s0; END IF; WHEN s1 = IF din=0 THEN state = s2; else state=s1; END IF; WHEN s2 = IF din=0 THEN state=s3; else state=s2; END IF; WHEN s3 = IF din=1 THEN state = s0; else state=s1; END IF; End Case; End if; End if; End process; op=1 when state=s1 else 0; END a; S0 S2 0/0 1/0 S3 1/0 S1 1/1 0/0 0/1 0/0 1/0 （2） Mealy型状态机 S0 S2 0/0 1/0 S3 1/1 S1 1/1 0/0 0/0 0/1 1/1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY mealy IS PORT( Clk,reset: IN STD_LOGIC; --clock din: IN STD_LOGIC; op: OUT STD_LOGIC); END mealy; ARCHITECTURE a OF mealy IS TYPE STATE_TYPE IS (s0, s1, s2,s3); SIGNAL state: STATE_TYPE; BEGIN S0 S2 0/0 1/0 S3 1/1 S1 1/1 0/0 0/0 0/1 1/1 PROCESS (clk,reset) BEGIN If reset = 1 THEN state = s0; else If clkEVENT AND clk = 1 then CASE state IS WHEN s0 = IF din=1 THEN state = s1; else state=s0; END IF; WHEN s1 = IF din=0 THEN state = s2; else