Code Generation of Nested Loops for DSP 基于DSP的嵌套功能循环的码发生器.pdfVIP

Code Generation of Nested Loops for DSP Processors with Heterogeneous Registers and Structural Pipelining WEI-KAI CHENG and YOUN-LONG LIN Tsing Hua University We propose a microcode-optimizing method targeting a programmable DSP processor. Effi- cient generation of microcodes is essential to better utilize the computation power of a DSP processor. Since most state-of-the-art DSP processors feature some sort of irregular architec- tures and most DSP applications have nested loop constructs, their code generation is a nontrivial task. In this paper, we consider two features frequently found in contemporary DSP processors — structural pipelining and heterogeneous registers. We propose a code generator that performs instruction scheduling and register allocation simultaneously. The proposed approach has been implemented and evaluated using a set of benchmark core algorithms. Simulation of the generated codes targeted towards the TI TMS320C40 DSP processor shows that our system is indeed more effective compared with a commercial optimizing DSP compiler. Categories and Subject Descriptors: C.3 [Computer Systems Organization]: Special-Pur- pose and Application-Based Systems—Real-time and embedded systems General Terms: Compiler Additional Key Words and Phrases: Code Generation, DSP 1. INTRODUCTION Many applications require performing various computationally-intensive digital signal processing (DSP) algorithms. When a pure software imple- mentation (on a general-purpose processor) cannot deliver adequate perfor- mance, users have to seek solutions in either ASIC or programmable DSP processors. While the ASIC approach can achieve the highest level of performance, the programmable DSP processor approach can lower design cost and shorten design time. In both cases, the microcode-ge