基于Verilog 的几种边沿探测方法的比较.docVIP

方法一：buf 缓冲检测法：该方法需要延迟2个clk时钟。 `timescale 1ns/1ps module rising_edge_check(clock, signal, rising_flag); input clock; input signal;//input signal output rising_flag;//rising edge flag reg [2:0] temp=3b000; always @(posedge clock) temp={temp[1:0],signal}; assign rising_flag=(temp[1:0]==2b01)?1b1:1b0; Endmodule `timescale 1ns/1ps module falling_edge_check(clock, signal, falling_flag); input clock; input signal; output falling_flag; reg [2:0] temp=3b111; always @(posedge clock) temp={temp[1:0],signal}; assign falling_flag=(temp[1:0]==2b10)?1b1:1b0; endmodule 边沿检测仿真波形： 双边沿检测： `timescale 1ns/1ps module double_edge_detect( clk, rst_n, data_in, raising_edge_detected, //上升沿检测 falling_edge_detected, //下降沿检测 double_edge_detected //双边沿检测 ); input clk; input rst_n; input data_in; output raising_edge_detected; output falling_edge_detected; output double_edge_detected; wire raising_edge_detected; wire falling_edge_detected; wire double_edge_detected; reg data_in_d1; //定义中间变量1 reg data_in_d2; //定义中间变量2 always @(posedge clk or negedge rst_n) begin if (rst_n == 1b0) begin data_in_d1 = 1b0; data_in_d2 = 1b0; end else begin data_in_d1 = data_in; data_in_d2 = data_in_d1; end end assign raising_edge_detected = data_in_d1 ~data_in_d2; // 上升沿检测输出 assign falling_edge_detected = ~data_in_d1 data_in_d2; //下降沿检测输出 assign double_edge_detected = data_in_d1 ^ data_in_d2; //双边沿检测输出 Endmodule 仿真波形：其中红色为双边沿检测仿真波形： 方法2：脉冲