一种锁定相位编程可调全数字锁相环设计（Design of locked phase programmable adjustable full digital phase locked loop）.docVIP

一种锁定相位编程可调全数字锁相环设计（Design of locked phase programmable adjustable full digital phase locked loop） A phase locked adjustable programming design of all digital phase locked loop 1 Introduction Phase lock technique has been widely used in signal processing, modulation, clock synchronization, frequency doubling, frequency synthesis and other fields. The realization of PLL are mainly analog phase-locked loop (APLL), all digital phase-locked loop (DPLL), digital analog phase-locked loop and delay locked loop (DLL) four. All digital phase-locked loop (DPLL) has high accuracy and is not affected by temperature and voltage, loop bandwidth and center frequency programming adjustable advantages has been widely used. The classical DPLL by digital phase discriminator, K mode, reversible counter pulse subtraction control circuit and the N divider is composed of 4 parts. The frequency of the input signal under the condition of stable, PLL lock timing output signal and input signal orthogonal. In the communication and many other application fields, not only need to keep the orthogonality relation between the output signal and the input signal, sometimes they need to maintain a certain phase difference. This slight improvement based on classical structure, puts forward the design of all digital phase-locked loop for the output signal and the input signal of the adjustable phase locking programming. Through computer simulation, FPGA implementation and board level system experiment, proved the feasibility and reliability of the system. 2 classic digital phase-locked loop structure and working principle Figure 1 shows the structure of the classical digital phase-locked loop by the discriminator of the XOR gate. The structure and function of each module: 2.1 XOR gate discriminator XOR gate discriminator will PLL Fin input signal and the output signal of Fout subtraction, output phase difference Se K mode as the counting direction of reversible counter signal. The output signal and the i