SILICON STARTING MATERIALS FOR SUB65nm （SUB65nm硅原料）.pdfVIP

SCP Symposium_June 2005_Seacrist SILICON STARTING MATERIALS FOR SUB-65nm TECHNOLOGY NODES Mike Seacrist MEMC Electronic Materials, St. Peters MO, 63376 Maintaining the pace of MOSFET device scaling has become increasingly difficult in the sub-100nm gate length regime. Increased chip functionality and device performance gains drive scaling. But, simple scaling of the channel length and gate oxide thickness is no longer sufficient to deliver the ~ 17% yearly speed / power performance enhancement target for high performance logic device technologies. Problems include short channel device effects such as sub-threshold leakage current and threshold voltage changes induced by the drain voltage (DIBL), and the high level of leakage current through the ultra-thin gate dielectric. These leakage currents cause higher static power dissipation. Active switching power is another key problem where a higher number of gates switching at high frequency with only modest reductions in supply voltage result in high active power density. The problems facing device scaling necessitate new solutions. The desired solution is one that enables continued critical dimension scaling at high yield, increases MOSFET drive current while reducing source to drain and gate leakage currents, reduces short channel effects, and reduces the active power density. The potential solution space includes changes in device fabrication materials, device architectures, and the silicon wafer starting materials. This paper will describe device problems faced for sub-65nm technology nodes. Potential silicon wafer solutions for sub-65nm technology nodes will be discussed and compared. Silicon wafer manufacturing considerations