PIC的TIMER2、ccp模块.pptVIP

8.3 TIMER2 模块(TIMER2 MODULE) TIMER2概述 Timer2 is an 8-bit timer with a prescaler and a postscaler(后分频). It can be used as the PWM time base for the PWM mode of the CCP module(s). The TMR2 （地址11h）register is readable and writable and is cleared on any device Reset. 8.3.1 TIMER2的原理框图 The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON1:0). The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit,TMR2IF (PIR11)). Timer2 can be shut-off by clearing control bit, TMR2ON (T2CON2), to minimize power consumption. 8.3.2 the Timer2 Control register bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 0010 = 1:3 postscale;… … 1111 = 1:16 postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 8.3.3 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: ? a write to the TMR2 register ? a write to the T2CON register ? any device Reset (POR, MCLR Reset, WDT Reset or BOR) TMR2 is not cleared when T2CON is written. 8.3.4 Output of TMR2 The output of TMR2 (before the postscaler) is fed to the SSP module, which optionally uses it to generate the shift clock. 8.3.5与TIMER2有关的REGISTERS 第11章CAPTURE/COMPARE/PWMMODULES 11.1 原理概述 Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: ? 16-bit Capture register ? 16-bit Compare register ? PWM Master/Slave Duty Cycle reg