路径延迟（Path delay）.docVIP

路径延迟（Path delay） One of the ways to check the timing is timing simulation, which calculates the delay values associated with the module during the simulation, and two is static timing verification. (1) delay type Distributed delay: defines a modeling method based on each individual component, assigning the delay value to a separate gate, and the other to specify a delay value in a separate assign statement. Total delay: defined on the basis of each individual module, it appears to be delayed when the module outputs the gate. It is easier to model than the distribution delay. Pin to pin (i.e. path) delay: assigning delays to each path between each input and each output of the module, respectively. As a result, delays can be specified for each input / output path, respectively. For large-scale circuits, it is easier to model than the distributed delay. The designer only needs to know the input and output pins of the module, so it is not necessary to understand the inner part of the module. (2) path delay Block specify: Module path delay: delay between the source and target pins of the module; assign the path delay between the keyword specify and the endspecify. Block contains: Specifies the lead to pin timing delay for all paths across the module, sets the timing check in the circuit, and defines the specparam constant. Cases: Module, M (out, a, B, C, D); Output out; Input, a, B, C, d; Wire, e, f; Specify (a=out) =9; (b=out) =9; (c=out) =11; (d=out) =11; Endspecify And, A1 (E, a, B); And, A2 (F, C, D); And, A3 (out, e, f); Endmodule The specify block is an independent part of the block that does not appear in any other module (such as initial or always), and the meaning of the internal statement must be very clear. Block specify internal: Parallel connection: each path statement has a source field and a target domain, each of which is connected to each other, if the vector must have the same number of bits, such as =delay_value (source=destination); Full connection: b