DSP课件 DSP Lecture2.ppt

CPU Interrupt Registers IFR IMR Note: 0 = Read as zeros, R = Read access, W = Write access, bit values are not affected by a device reset BIT IFR 中断标志寄存器 IMR 中断屏蔽寄存器 Bit 15-6 Reserved Reserved Bit 5 INT6. Interrupt 6 flag. The flag for interrupts connected to interrupt level INT6. 0 No INT6 interrupt is pending. 1 At least one INT6 interrupt is pending. Write a 1 to this bit to clear it to 0 and clear the interrupt request. INT6. Interrupt 6 mask. This bit masks or unmasks interrupt level INT6. 0 Level INT6 is masked. 1 Level INT6 is unmasked. Bit 4 - 0 The flags for INT5, INT4, INT3, INT2, INT1, with the same meaning as in the description for INT 6. The masks for INT5, INT4, INT3, INT2, INT1, with the same meaning as in the description for INT6 Peripheral Interrupt Registers The peripheral interrupt vector register (PIVR) The peripheral interrupt request register 0 (PIRQR0) The peripheral interrupt request register 1 (PIRQR1) The peripheral interrupt request register 2 (PIRQR2) The peripheral interrupt acknowledge register 0 (PIACKR0) The peripheral interrupt acknowledge register 1 (PIACKR1) The peripheral interrupt acknowledge register 2 (PIACKR2) PIVR V15–V0. Interrupt vector. This register contains the peripheral interrupt vector of the most recently acknowledged peripheral interrupt. During the peripheral interrupt acknowledge cycle, the PIVR is loaded with the interrupt vector of the highest-priority pending interrupt associated with the CPU interrupt (INTn) being acknowledged (or the phantom interrupt vector). PIVR 701Eh Peripheral Interrupt Request Registers (PIRQR0, 1, 2) PIRQR0 7010h PIRQR continued1… PIRQR1 7011h PIRQR continued2… PIRQR2 7012h Peripheral Interrupt Acknowledge Registers (PIACKR0 ,1, 2) PIACK0 7014h Same interrupt sequence as defined in PIRQR0 PIACKR continued1 … PIACK1 7015h PIACK2 7016h External Interrupt Control Registers XINT1CR 7070h XINT2CR 7071h BIT XINT1CR XINT2CR Bit 15 XINT1 Flag This bit indicates whether the sel