多晶矽无接面电晶体技术-国家奈米元件试验室.PDF

020 Poly-Si Junctionless Device Technology 1 2 1 1,3 1 2 3 3D Abstract An in situ doped silicon layer was deposited to serve as the channel of nanowire and planar junctionless transistor. The concentration and doping type of channel is identical to that of source and drain for junctionless transistors. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. Due to high concentration, the junctionless transistors exhibit superior electrical characteristics in terms of higher on/o current ratio and lower source/drain resistance. Such a scheme shows a promising alternative for the future application of 3D-ICs and at panel products. Keywords Junctionless (JL) poly-Si, Nanowire (NW) Non-volatile Memory (NVM) Thin-film Transistor NANO COMMUNICATION 21 No. 1