中断机制（The interrupt mechanism）.docVIP

中断机制（The interrupt mechanism） If you use an SD card or NandFlash, you will use ROMCode, and the interrupt vector starts at 0x14000, which in turn is Reset, Undef, Prefetch Abort, Data Abort, Data Abort, reservation, IRQ, FIQ. For example, an IRQ interrupt occurs when the program automatically jumps to 0x14018. The following is an example of IRQ: (1) when IRQ is interrupted, the program counter PC jumps to 0x14018. (2) ROMCode immediately lets PC jump to the RAM interrupt vector starting at 0x0x4020FFC8. Notice that the Reset interrupt directly executes ROMCode without the RAM interrupt vector, so the RAM interrupt vector starts with Undef and IRQ is 0x4020FFDC (3) in all of these are stored in RAM interrupt vector a PC = [RAM interrupt vector address + 0 x1c] instruction (note the brackets meaning is take the contents of the address), the work is done by ROMCode normal startup, but when I was writing code or back to the side, for IRQ, RAM interrupt vector address + 0 x1c = 0 x4020ffdc + 0 x4020fff8 x1c = 0 (4) so you only need to store the address of your IRQ function at 0x4020FFF8, and in my OclO, CPU/omap-3 / start.s has some code: AwSRAMVectorBase: The word SRAM_VECTORS_BASE SRAM_VECTORS_BASE is defined in include/asm/arch - omap3 / omap35x.h # define SRAM_VECTORS_BASE 0x4020FFC8 / / interrupt table address specified by Rom Code LDR r1, awSRAMVectorBase / * build vect addr * / Next: Ldmia r0! , {r3 - r9} / * copy from source address [r0] * / Stmia r1! , {r3 - r9} / * copy to target address [r1] * / CMP r0, r2 / * until source end address [r2] * / Bne Next / * loop until equal * / The above loop is to put all the interrupted response function first address to the address of the response, and when the PC = [RAM interrupt vector address + 0x1C], it can jump into the function of the response. Each function consists of two parts: assembly + C, and the assembly section is in stars.s IRQ for IRQVectorA: STMFD sp! , {r0 - r12, lr} Bl IRQVectorC LDMFD sp! , {r0 - r12, lr