lcd 1602 VHDL程序编写(virtex4开发板).docxVIP

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity lcd isport(rst,sysclk:in std_logic; lcd_e,lcd_rs,lcd_rw:out std_logic; lcd_db:out std_logic_vector(3 downto 0));end lcd;architecture Behavioral of lcd istype states is(start,start1,start2,start3,start4,wait1,wait2,wait3,clear_display1,clear_display2,set_function1,set_function2,set_display1,set_display2,set_entrymode1,set_entrymode2, write_data1,write_data2,write_data3,write_data4,write_data5,write_data6,set_ddram1,set_ddram2,done); signal current_state,next_state:states; signal clock:std_logic:=0; signal counter:integer range 0 tobegin lcd_rw=0; process(sysclk) begin if rising_edge(sysclk) thenif counterthen counter=0; clock=NOT clock;else counter=counter+1; end if; end if;end process;lcd_e=clock;process(clock,rst)begin if (rst=0) then current_state=start; elsif rising_edge(clock) then current_state=next_state; end if;end process;process(current_state)begincase current_state is when start= next_state=wait1; when wait1= lcd_rs=0; next_state=start1; when start1= lcd_rs=0; lcd_db=0011; next_state=start2; when start2= lcd_rs=0; lcd_db=0011; next_state=start3; when start3= lcd_rs=0; lcd_db=0011; next_state=start4; when start4= lcd_rs=0; lcd_db=0010; next_state=set_function1;when set_function1= lcd_db=0010; lcd_rs=0; next_state=set_function2; when set_function2= lcd_db=1000; lcd_rs=0; next_state=set_entrymode1; when set_entrymode1= lcd_db=0000; lcd_rs=0; next_state=set_entrymode2; when set_entrymode2= lcd_db=0110; lcd_rs=0; next_state=set_display1; when set_display1= lcd_db=0000; lcd_rs=0; next_state=set_display2; when set_display2= lcd_db=1100; lcd_rs=0; next_state=clear_display1; when clear_display1= lcd_db=0000; lcd_rs=0