数码锁实验报告.docVIP

数码锁设计 设计方案： 用层次化混合输入的方法来设计数码锁，底层模块用Verilog HDL来，顶层模块采用原理图。顶层采用的原理图分成三大模块：控制模块、输入模块和判断模块；按照这的大致方向先设计好三大底层模块，生成元器件，再在顶层设计上将其一步一步连接，最后实现系统的整体功能。 图1 数码锁顶层总设计 设计过程： 按照预先设计的方案分别进行控制模块、输入保存模块和判决模块三大模块的程序设计。 控制模块： module control(unlock,setup,start,open,clr_singal,open_singal); input setup,start,open,unlock; output clr_singal,open_singal; reg clear_flag,setup_en,start_en,open_en; always @(posedge setup or posedge unlock) begin if(unlock) setup_en=0; else setup_en=1; end always @(posedge start) begin if(setup_en) start_en=1; end assign clr_singal=startsetup_en; assign open_singal=openstart_en; endmodule 输入模块： module input_code(k,start,out1,out2,out3); input[9:0] k; input start; output[3:0] out1,out2,out3; reg in; reg[3:0] code,out1,out2,out3; reg[2:0] state; always @(k) begin case(k) 10b00_0000_0001:begin code=4h0;in=1;end 10b00_0000_0010:begin code=4h1;in=1;end 10b00_0000_0100:begin code=4h2;in=1;end 10b00_0000_1000:begin code=4h3;in=1;end 10b00_0001_0000:begin code=4h4;in=1;end 10b00_0010_0000:begin code=4h5;in=1;end 10b00_0100_0000:begin code=4h6;in=1;end 10b00_1000_0000:begin code=4h7;in=1;end 10b01_0000_0000:begin code=4h8;in=1;end 10b10_0000_0000:begin code=4h9;in=1;end default:begin code=4ha;in=0;end endcase end always @(posedge start or posedge in) begin if(start) begin state=0; out1=4hb; out2=4hb; out3=4hb; end else begin case(state) 0:begin out1=code;state=1;end 1:begin out2=code;state=2;end 2:begin out3=code;state=3;end endcase end end endmodule 判断模块： Module judgement(lock,led1,spk,led2,lock_system,setup,I_setup,open,c1,c2,c3,code1,code2,code3); input open,I_setup,setup; input[3:0] c1,c2,c3,code1,code2,code3; output lock,led1,spk,led2,lock_system; reg lock,led1,spk,led2,lock_system; reg clear; always @(posedge setup or posedge I_setup or posedge open) begin if(setup)