EDA数字电压表设计.docVIP

数字电压表源程序： module shuzidianya(ale,start,oe,addr,seg,d,eoc,clk,clk1k); output ale,start,oe; //通道锁存，转换开始，输出允许 output[2:0] addr; //通道选择 output[7:0] seg; //数码管段选 input[7:0] d; //转换结果输入 input eoc,clk,clk1k; //转换结束 wire[7:0] q; wire[3:0] dec_in; adcint(ale,start,oe,addr,q,d,clk,eoc); segscan segscan(dec_in,q,clk1k); decoder decoder(seg,dec_in); endmodule //ADC0809控制模块 module adcint(ale,start,oe,addr,q,d,clk,eoc); output ale,start,oe; output[2:0] addr; output[7:0] q; input[7:0] d; input clk,eoc; reg ale,start,oe; reg[7:0] q; reg lock; reg[4:0] present_state,next_state; parameter st0=5b00001, st1=5b00010, st2=5b00100, st3=5b01000, st4=5b10000; assign addr=3b000; always @(posedge clk) begin present_state=next_state; end always @(present_state or eoc) begin case(present_state) st0:next_state=st1; st1:next_state=st2; st2: begin if(eoc) next_state=st3; else next_state=st2; end st3:next_state=st4; st4:next_state=st0; default:next_state=st0; endcase end always @(present_state) begin case(present_state) st0:begin ale=0;start=0;lock=0;oe=0;end st1:begin ale=1;start=1;lock=0;oe=0;end st2:begin ale=0;start=0;lock=0;oe=0;end st3:begin ale=0;start=0;lock=0;oe=1;end st4:begin ale=0;start=0;lock=1;oe=1;end default begin ale=0;start=0;lock=0;oe=0;end endcase end always @(posedge lock) begin q=d; end endmodule module weisaomiao(clk,sel1); input clk; output [1:0]sel1; reg [1:0]sel1; always @(posedge clk ) begin sel1=sel1+1; end endmodule module suocun( qo, din, load ); output[7:0] qo; input[7:0] din; input load; reg[7:0] qo; always @( posedge load ) begin qo = din; end endmodule module segscan(dout,din,sel); output[3:0] dout; input [7:0] din; input sel; reg[3:0] dout; always @(sel or din) begin if (sel) dout=din[3:0]; else dout=din[7:4]; end endmodule //显示译码模块 module decoder(decoderout,dec_in); output[7:0] decoderout; input[3:0] dec_in; reg[7:0] decoderout; always @(dec_in) begin