SlidesPreparedfromtheCI-TutorCoursesatNCSAhttpci-摘要.pptVIP

IBM p690 General Overview The p690 is IBMs latest Symmetric Multi-Processor (SMP) machine with Distributed Shared Memory (DSM). This means that memory is physically distributed and logically shared. It is based on the Power4 architecture and is a successor to the Power3-II based RS/6000 SP system. IBM p690 Scalability The IBM p690 is a flexible, modular, and scalable architecture. It scales in these terms: Number of processors Memory size I/O and memory bandwidth and the Interconnect bandwidth Agenda 9 About the IBM Regatta P690 9.1 IBM p690 General Overview 9.2 IBM p690 Building Blocks 9.2.1 Power4 Core 9.2.2 Multi-Chip Modules 9.2.3 The Processor 9.2.4 Cache Architecture 9.2.5 Memory Subsystem 9.3 Features Performed by the Hardware 9.4 The Operating System 9.5 Further Information IBM p690 Building Blocks An IBM p690 system is built from a number of fundamental building blocks. The first of these building blocks is the Power4 Core, which includes the processors and L1 and L2 caches. At NCSA, four of these Power4 Cores are linked to form a Multi-Chip Module. This module includes the L3 cache and four Multi-Chip Modules are linked to form a 32 processor system (see figure on the next slide). Each of these components will be described in the following sections. 32-processor IBM p690 configuration (Image courtesy of IBM) Power4 Core The Power4 Chip contains: Two processors Local caches (L1) External cache for each processor (L2) I/O and Interconnect interfaces The POWER4 chip(Image curtsey of IBM) Multi-Chip Modules Four Power4 Chips are assembled to form a Multi-Chip Module (MCM) that contains 8 processors. Each MCM also supports the L3 cache for each Power4 chip. Multiple MCM interconnection (Image courtesy of IBM) The Processor The processors at the heart of the Power4 Core are speculative superscalar out of order execution chips. The Power4 is a 4-way superscalar RISC architecture running instructions on its 8 pipelined execution unit