COA课件17.pptVIP

※17.3 Cache Coherence  and MESI Protocol Cache一致性和 MEIS协议 Problem - multiple copies of same data in different caches (each CPU read or write a data) Read: —Read hit (CacheMemory have the data) —Read miss (the data from Memory is mapped into Cache) = in Cache in Memory, the data is the same. It is not relation with other CPU Page 656(640) Write: —Write hit (the data in Cache is different with Memory) —Write miss(mapping data from memory or other Cache ) after fetching data, rewrite data in Cache =Can result in an inconsistent view of memory Chapter4 two write policies: Write back polity means write operation to main memory only when the relative cache is replaced Write back policy can lead to inconsistency Write through polity means write operation to main memory as well as to cache Write through can also give problems unless caches monitor memory traffic Software Solutions Compiler and operating system deal with problem Page 657(640) Hardware Solution Cache coherence protocols More efficient ,Transparent(透明的) to programmer Directory protocols目录协议 Snoopy protocols 监听协议 Page 658(641) Snoopy Protocols(1) 监听协议 Two basic approaches to snoopy protocol have been explored： —Write invalidate 写—无效协议 —Write update 写—更新协议 Write Update Multiple readers and writers Updated word is distributed to all other processors(all update at the same) 写—更新协议 Write Invalidate Multiple readers, one writer When a write is required, all other caches of the line are invalidated Writing processor then has exclusive (cheap) access until line required by another processor Used in Pentium II and PowerPC systems State of every line is marked as Modified, Exclusive, Shared or Invalid MESI 写—无效协议 The MESI Protocol(1) The data cache includes two status bits per tag So each line can be in one of four states： Modified (修改态 ) —The line in the cache has been modified(different from main memory) and available only in this cache (只有此cache中数据行的有效 ) Exclus