如何提高fpga速度(国外英文资料).docVIP

如何提高fpga速度(国外英文资料) For designers, of course we want the frequency of the circuits we design (no special instructions here, and the operating frequency means the working frequency in the FPGA chip) as high as possible. We also often hear that using resources for speed, and using water to improve the frequency of work, this is indeed a very important method, today I would like to further analyze how to improve the frequency of the circuit. Lets first analyze what affects the frequency of the circuit. The operating frequency of our circuit is mainly related to the signal propagation delay between registers and registers and clock skew. Within the FPGA, if the clock goes long, the clock skew is small and basically ignored. Here, for simplicitys sake, we only consider the propagation delay factor of the signal. The propagation delay of the signal including switch delay, register wire delay, after a delay of combinational logic (this division may not be accurate, but it should be no problem for analysis, can) to improve the working frequency of the circuit, we should do in this three delay, make it as small as possible. Lets switch delay, the delay is determined by the physical characteristics of the device, we have no way to change, so we can only go through the change of line and reduce the method of combinational logic to improve the working frequency. 1. reduce the delay by changing the way the line is traveled. The Altera device as an example, we quartus inside the timing closure floorplan can see a lot of different departments and regions, we can been controlled by rows and column points, each block represents 1 LAB, each LAB has 8 or 10 LE. Their routing delay relationships are as follows: the same LAB (fastest) column or peer different rows and different columns. We add the appropriate constraint to the synthesizer (can not be greedy, generally with 5% margin is more appropriate, such as circuit in 100Mhz, and 105Mhz can be added to the constraint, the greedy ef