用VHDL编写的二进制除法器（国外英文资料）.docVIP

用VHDL编写的二进制除法器（国外英文资料） 图书馆ieee; 使用ieee.std_logic_1164.all; 使用ieee.std_logic_unsigned.all; 使用ieee.std_logic_arith.all; 实体DIV 通用(BN:整数:= 6); 端口( 在std_logic SYSClk:; 重置:std_logic; BCS:在std_logic_vector(bn - 1 downto 0); CS:std_logic_vector(BN-1报纸0); 裁判:std_logic; STD_LOGIC W_CLK:; SH_H:std_logic_vector(BN-1报纸0); YS_H:out std_logic_vector(bn - 1 downto 0) ); DIV结束; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - DIV的架构rtl 信号YS_N:STD_LOGIC_VECTOR(bn - 1 downto 0); 信号y:STD_LOGIC_VECTOR(bn - 1 downto 0); 信号REF_N:std_logic; 信号W_CLK_N:STD_LOGIC; 信号按:STD_LOGIC; 信号PRESS_N:STD_LOGIC; 信号reg_b:std_logic_vector(BN-1报纸0); 信号reg_b_N:std_logic_vector(BN-1报纸0); 信号reg_c:std_logic_vector(BN-1报纸0); 信号reg_c_N:std_logic_vector(BN-1报纸0); 信号数:std_logic_vector(5报纸0); 信号COUNT_N:std_logic_vector(5报纸0); 临时的信号:std_logic_vector(BN报纸0); 信号temp_n:std_logic_vector(BN报纸0); 信号加:std_logic_vector(BN降至0); 信号PLUS_N:std_logic_vector(BN降至0); 信号状态:STD_LOGIC; 信号STATE_N:STD_LOGIC; ——信号REG_B_N:STD_LOGIC_VECTOR(bn - 1 downto 0); 信号SH:STD_LOGIC_VECTOR(bn - 1下降到0); 信号SH_N:STD_LOGIC_VECTOR(bn - 1 downto 0); 开始 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 过程(SYSCLK重置) 开始 如果重置= 0 COUNT =(其他人= 0 ); 然后是elsif(SYSCLK event和SYSCLK = 1) 数 = COUNT_N; 如果; 结束过程; 过程(状态,计算) 开始 如果状态= 1 COUNT_N = COUNT + 1; 其他的 COUNT_N =(其他人= 0 ); 如果; 结束过程; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -