Verilog HDL进门基础之时序状态机的设计(国外英文资料).docVIP

Verilog HDL入门基础之时序状态机的设计(国外英文资料) Introduction and improvement of timing machine Computer and perform a series of information stored in the storage or in accordance with the operation of other digital system are collectively referred to as sequence state machine, the circuit can use temporal logic modeling. Sequence state machine performance and combinational logic is different, because the sequence state machine output depends not only on the current input values, but also depends on the input value of history. Sequential state machines are widely used in applications that require sequential operations. All the sequence state machine with general feedback structure, as shown in figure in this kind of structure sequence state machine to the next state is formed by the current state and the current input together: The sequential state machine can be divided by a common clock control (clock control) into the synchronous state machine and the asynchronous state machine; According to the state number, finite state machine and infinite state machine. Only finite state machines are discussed here. Classification of finite state machine (FSM) The finite state machine has the Mealy machine and Moore machine: Mealy machine: The next state and output of the Mealy machine depend on the current state and current input. Moore (Moore) machine: The next state of the Moore machine depends on the current state and the current input, and the output depends only on the current state. The description and development method used by the finite state machine Finite state machines can be described and designed using sequence diagrams, state tables, state diagrams, and ASM diagrams. ? The sequence diagram can be used to illustrate the relationship between the effective input and the state transfer of the signal in the system and the interface between the system and the surrounding environment. ? The status table and the state transition table represent the next state and output of the state