论文原理说明及仿真结果.doc

RFID系统反碰撞算法设计与FPGA仿真 郭 旭 峰 摘　要 近几年来，RFID(Radio Frequency Identification)技术在全球掀起热潮，吸引了众多厂商参与相关的技术以及芯片的研究与开发。目前RFID技术正处于迅速上升的时期。在很多实际应用中读写器的识读范围内会同时出现多个标签。这时标签发送的信息就会混叠在一起发生冲突，产生碰撞问题。这就要求RFID系统有一个解决碰撞问题的高效反碰撞算法，在某些苛刻的应用中，要求RFID系统碰撞算法具有很高的处理速度，这就需要由硬件来实现算法，以达到高速实时处理的要求。FPGA器件为此提供了很好的解决方案。 在本文中，着重研究了RFID系统的反碰撞算法，阐述了一种快速高效的RFID系统反碰撞算法——跳跃式二进制树形算法的工作原理，并完成了算法的Verilog HDL语言设计和FPGA仿真。算法执行时，识别出标签的时隙称为有效时隙，有效时隙与总时隙的比值即为算法的执行效率。理论及实验数据证明，随着标签数目的增多，这种跳跃式二进制树形算法的效率稳定在50％。基于ISO 14443对通信速率的规定，通过仿真，单台读写器的最快识别速度可达212个标签/秒。 关键词：RFID, 反碰撞， 二进制树形， FPGA Anti-collision algorithm design and FPGA simulation for RFID System Author: GUO Xu-feng Abstract With the advocation of some international institutes and companies the RFID (Radio Frequency Identification) technology has recently played an important role in lots of fields. A number of companies have taken part in the research of RFID technology and standards, and the technology of RFID is developing very fast. In some applications many tags exist in the field of reader-writer at a same time. At this moment the signals sent from the tags interact, and this case is named collision.So a high permormance anti-collision algorithm is needed to solve the collision problem. In some occasions hardware is required to execute the algorithm to improve the executing efficiency. Using FPGA to execute the anti-collision algorithm is one of the best ways to solve this problem. In this paper, firstly research the anti-collision algorithm has been focused on. A high performance anti-collision algorithm, jumping binary tree-like anti-collision algorithm, was designed using Verilog HDL and was simulated with FPGA as well. When the algorithm is running, the time-slots in which tag has been identified is defined as effective time-slot, the ratio between effective time-slot and total time-slot is defined as the efficiency of the algorithm. Theoretic analysis and simulation results have proved that the efficiency of this anti-collision algorithm remains at 50