用VHDL语言实现的数码管显示程序〔包含动态和静态〕.docVIP

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity shumaguan is port(clk:in std_logic; x:out std_logic_vector(7 downto 0); seg:out std_logic_vector(7 downto 0)); end entity; architecture behave of shumaguan is signal clk1:std_logic; begin process(clk) variable count:integer range 0 to begin if(clkevent and clk=1) then if(count then --动态 --if(count=1000) then --静态 count:=0; clk1=not clk1; else count:=count+1; end if; end if; end process; process(clk1) variable a:integer range 1 to 8; begin if(clk1event and clk1=1) then if(a=8) then a:=1; else a:=a+1; end if; end if; case a is when 1=xseg when 2=xseg when 3=xseg when 4=xseg when 5=xseg when 6=xseg when 7=xseg when 8=xseg when others=null; end case; end process; end behave;