FPGA实现DSP系统的结构模型.pptVIP

FPGA嵌入式系统设计;第三章 基于模型的设计技术;3.1 SYSGEN简介; 系统设计所面临的挑战;传统设计流程;Traditional Simulink FPGA Flow;The Elements of Model-Based Design ;System Generator for DSP Platform Designs;System Generator for DSP v8.1;Model-Based Design with Simulink ;基于模型设计的优点;MATLAB Simulink;带有仿真的设计 Design with Simulation;带有仿真的设计 Design with Simulation;由自动代码生成进行实现 Implementation with Automatic Code Generation;由自动代码生成进行实现 Implementation with Automatic Code Generation;持续的测试和校验Continuous Test and Verification;设计流程和工具;Simulink模型硬件实现;系统设计模型到FPGA VHDL目标代码-Xilinx;系统设计模型到FPGA VHDL目标代码-Altera;3.2 基于模型的设计流程 FPGA实现DSP;利用FPGA实现DSP;数字信号处理技术; FPGA 结构与资源;FPGA实现DSP的软件工具 ;通用DSP-单引擎乘法累加;FPGA-多引擎乘法累加;动态系统建模与分析Modeling and Analysis of Dynamic Systems;系统建模Modeling the System;模型求解Solving the Model ;SysGen 流程;The SysGen Design Flow;;System Generator Based Design Flow;System Generator Based Design Flow;设计流程-重要概念之一;;;Gateway In/Out;The Xilinx Blocks;The Concat Block;The Convert Block;The Convert Block;The Convert Block;The Convert Block;The Reinterpret Block;The Reinterpret Block;The Slice Block;The Slice Block;The Slice Block;What Values Do You Expect?;Module 5: What Values Do You Expect?;基于模型设计流程实例:FIR滤波器设计 ;Creating a System Generator Design;Finding Blocks;System Generator Design;Creating a SystemGenerator Design;产生FIR滤波器的系数 ;系数与FIR滤波器关联 ;模块参数设置 ;在Simulink中仿真FIR滤波器 ;重要概念之二——采样周期;The Simulink System Period MUST be set in the System Generator token. For single rate systems it will be the same as the Sample Periods set in the design. More on Multi Rate designs later;SysGen Token;启动仿真;完善FIR滤波器设计 ;Input : Width = FIX_8_6, Quantization = Truncate, Overflow = Wrap Output Width: FIX_8_6 FIR Core Latency: 14 FIR Hardware Over-Sampling Rate: 9 FIR Coefficients: FIX_12_12 Product Family: Virtex-II Pro Device: xc2vp30 Speed: 7 Package: ff896 Synthesis Tool: XST Target Directory: F:/ sysgenlab/lab2 Create Testbench: Unchecked Simulink System Period (sec): 7.407e-008 FPGA System Clock Period (ns): 10;3.3 硬件协同仿真技术HDL