DIGITALCP8.pptVIP

CHAPTER 8 FLIP-FLOPS AND RELATED EDVICES;Astable (非稳态的 ) Hold-time ( 保持时间 ) Asynchronous ( 异步 ) Bistable ( 双稳态 ) Clear ( 清零 ) D flip-flop ( D 触发器 ) Edge-triggered flip-flop ( 边沿触发器 ) Feed-back ( 反馈 ) Hysteresis ( 迟滞 ) J-K flip-flop ( J—K触发器 ) Latch ( 锁存器 ) Master-slave flip-flop ( 主从触发器 ) ;Monostable ( 单稳态 ) One-shot ( 单稳 ) Preset ( 预置1 ) RESET ( 置0 ) SET ( 置1 ) Set-up time ( 设置时间 ) S-R flip-flop ( R—S触发器 ) Synchronous ( 同步 ) Timer ( 计时器 ) Toggle ( 触发 , 计数 ) ;KEY TERMS ;Clear An asynchronous input used to reset a flip-flop ( make the Q output 0 ). D flip-flop A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse.;Edge-triggered flip-flop A type of flip-flop in which the data are entered and appear on the output on the same clock edge. Feedback The output voltage or a portion of it that is connected back to the input of a circuit.;Hold time The time interval required for the control levels to remain on the inputs to a flip-flop after the triggering edge of the clock in order to reliably activate the device. Latch A bistable digital circuit used for storing a bit.;Hystersis A characteristic of a threshold-triggered circuit, such as the Schmitt trigger, where the device turns on and off at different input levels. J-K flip-flop A type of flip-flop that can operate in the SET, RESET, no-change, and toggle modes.;Master-slave flip-flop A type of flip-flop in which the input data are entered into the device on the leading edges of clock pulses and apper at the output on trailing edges. Master-slave flip-flops have, for the most part, been replaced by edge-triggered types.;Monostable Having only one stable state. A monostable multivibrator, commonly called a one-shot, produ