7.1宏功能模块概述.ppt

EDA技术与VHDL ;7.1 宏功能模块概述 ;7.1 宏功能模块概述 ;7.1 宏功能模块概述 ;7.1 宏功能模块概述 ;7.2 LPM模块应用实例 ;7.2 LPM模块应用实例 ;7.2 LPM模块应用实例 ;7.2 LPM模块应用实例 ;7.2.2 定制LPM_ROM初始化数据文件 ;7.2.2 定制LPM_ROM初始化数据文件 ;7.2.3 定制LPM_ROM元件 ;7.2.3 定制LPM_ROM元件 ;7.2.3 定制LPM_ROM元件 ;7.2.3 定制LPM_ROM元件 ;7.2.3 定制LPM_ROM元件 ;7.2.3 定制LPM_ROM元件 ;【例7-3】修改后的用于例化的波形数据ROM文件：data_rom.vhd LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; --使用宏功能库中的所有元件 ENTITY data_rom IS PORT (address : IN STD_LOGIC_VECTOR (5 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END data_rom; ARCHITECTURE SYN OF data_rom IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram --例化altsyncram元件，调用了LPM模块altsyncram GENERIC ( --参数传递语句 intended_device_family : STRING; --类属参量数据类型定义 width_a : NATURAL; widthad_a : NATURAL; numwords_a : NATURAL; operation_mode : STRING; outdata_reg_a : STRING; address_aclr_a : STRING; outdata_aclr_a : STRING; width_byteena_a : NATURAL; init_file : STRING; lpm_hint : STRING; lpm_type : STRING ); PORT ( clock0 : IN STD_LOGIC ; --altsyncram元件接口声明 address_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT;; 【例7-3】 BEGIN q = sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( intended_device_family = Cyclone, --参数传递映射 width_a = 8, --数据线宽度8 widthad_a = 6, --地址线宽度6 numwords_a = 64, --数据数量64 operation_mode = ROM, --LPM模式ROM outdata_reg_a = UNREGISTERED, --输出无锁存 address_aclr_a = NONE, --无异步地址清0 outdata_aclr_a = NONE,