Lecture12-InverterDelay+Energy.pdfVIP

EE141 1 EE141 EECS141 1 Lecture #12 EE141 EECS141 2 Lecture #12 ?? HW 4 Due Today. New HW today as well. ?? Final Lab next week ?? Project to be launched on Wednesday! Probably is wise to be in class that day. EE141 2 EE141 EECS141 3 Lecture #13 EE141 EECS141 4 Lecture #13 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 V in (V) V o ut (V ) Wider PMOS Wider NMOS Symmetrical EE141 3 EE141 EECS141 5 Lecture #13 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 V in (V) V o ut (V ) Fast PMOS Slow NMOS Fast NMOS Slow PMOS Nominal EE141 EECS141 6 Lecture #13 Not all transistors are alike Impacts parameters such as reliability and performance Define process corners: SS, FF, SF, FS EE141 4 EE141 EECS141 7 Lecture #13 7 EE141 EECS141 8 Lecture #13 ?? We modeled this with: C ?? Discharging a capacitor tp = ln (2) RC EE141 5 EE141 EECS141 9 Lecture #13 ??Real transistors aren’t exactly resistors ?? Look more like current sources in saturation ??Two questions: ?? Which region of IV curve determines delay? ?? How can that match up with the RC model? EE141 EECS141 10 Lecture #13 ?? With a step input: ID VDS VDD VDD /2 VGS = VDD VDD ? VDD/2 VVSAT ?? Transistor is in (velocity) saturation during entire transition from VDD to VDD/2 EE141 6 EE141 EECS141 11 Lecture #13 ?? In saturation, transistor basically acts like a current source: IDSAT C VOUT VOUT = VDD - (IDSAT/C)t VOUT t VDD VDD/2 tp tp = C(VDD/2)/IDSAT EE141 EECS141 12 Lecture #13 EE141 7 EE141 EECS141 13 Lecture #13 ?? Including output conductance: ?? For “small” λ: IDSAT C VOUT 1/(λIDSAT) EE141 EECS141 14 Lecture #13 ?? Transistor current not linear on VOUT – how is the RC model going to work? ?? Look at waveforms: ?? Voltage looks like a ramp for RC too EE141 8 EE141 EECS141 15 Lecture #13 ?? Match the delay of the RC model with the actual delay: ?? Often just: ?? Note that the book uses a different method and gets 0.75·VDD/