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A Fractional-N CMOS DPLL with Self-Calibration
第 26 卷 第 11 期
2005 年 11 月
半 导 体 学 报
CHIN ESE J OURNAL OF SEMICONDUCTORS
Vol. 26 No. 11
Nov. ,2005
3 Project supported by t he National High Technology Research and Development Program of China (No. 2002AA1Z1290)
Liu Sujuan female ,was born in 1978 ,PhD candidate. Her research interest s are CMOS analog and mixed integrated circuit s design.
Yang Weiming male ,was born in 1969 ,PhD candidate. His research interest is RF circuit s design.
Chen Jianxin male ,was born in 1946 ,professor ,advisor of PhD candidates. His research fields involve high2speed microelect ronics and inte2
grated circuit s design.
Received 27 November 2004 ,revised manuscript received 25 J uly 2005 Ζ 2005 Chinese Institute of Elect ronics
A Fractional2N CMOS DPLL with Self2Calibration 3
Liu Sujuan
1
, Yang Weiming
1
, Chen Jianxin
1
, Cai Liming
2
, and Xu Dongsheng
2
(1 O ptoelect ronics L aboratory , Bei j ing Universit y of Technology , Bei j i ng 100022 , China)
(2 China I ntegrated Ci rcuit Desi gn Center , B ei j ing 100015 , China)
Abstract : A digital phase2locked loop (DPLL ) based on a new digital phase2f requency detector is p resented. The
self2calibration technique is employed to acquire wide lock range ,low jitter ,and fast acquisition. The DPLL works
f rom 60 to 600M Hz at a supply voltage of 118V. It also features a f ractional2N synthesizer with digital 2nd2order sig2
ma2delta noise shaping ,which can achieve a short lock time ,a high frequency resolution ,and an improved phase2noise
spectrum. The DPLL has been implemented in SMIC 0118μm 118V 1P6M CMOS technology. The peak2to2peak jitter
is less than 018 % of the output clock period and the lock time is less than 150 times of the reference clock period af2
ter the pre2divider.
Key words : digital phase2locked loop ; phase2f requency detector ; self2calibration ; voltage controlled oscillator ;
f ractional2N
EEACC : 2570
CLC number : TN431 Document code : A Article ID : 025324177 (2005) 1122085207
1 Introduct
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