SynthesizablemodelofAtmelATmega103microcontroller.docVIP

Synthesizable model of Atmel ATmega103 microcontroller. For the moment the model consists of the following blocks: 1. AVR core. 2. Program memory. 3. Data memory. 4. UART. 5. Timer/Counter. 6. PORTA and PORTB. Limitations. Core limitations : For the moment the core doesnt support SLEEP and CLRWDT instructions. UART limitations : No (I hope!). Timer/Counter limitations: For the moment only Timer/Counter0 and Timer/Counter2 are implemented. Timer/Counter0 emulates the asynchronous mode (The Timer/Counter0 of Atmega103 microcontroller operates with two separate clock sources). Timer/Counter0(Timer/Counter2) supports toggling of OC0/PWM0(OC0/PWM2) output line , but doesnt support set/reset of this line. PORTA and PORTB limitations: PORTA and PORTB operate as parallel ports only and dont support additional functions (OCx/PWMx , #INTx, etc.). Additional features. A simple timer was added to the model for the sake of test only. It generates interrupt request(INT0) every 256 cycles of cp2. Brief description of project structure. AVR core: avr_core.vhd - top level design of AVR core alu_avr.vhd - ALU bit_processor.vhd - some bit operations reg_file.vhd - register file pm_fetch_dec.vhd - main part of the core (instruction decoder, memory and I/O interfaces, PC, etc.) io_reg_file.vhd - I/O registers implemented inside the core(SREG, RAMP, SPH, SPL) io_adr_dec.vhd - address decoder and data bus multiplexer for the I/O registers implemented inside the core Microcontroller: top_avr_core_sim.vhd - top level design of microcontroller(for simulation) AVRuCPackage.vhd - constants and types external_mux.vhd - data bus multiplexer RAMDataReg.vhd - data bus register PROM.VHD - program memory(for simulation) DataRAM.vhd - data