EDA技术与VHDL课后答案(版)潘松黄继业.docVIP

第3章 VHDL基础 习题 3-1 如图所示 3-2 程序： IF_THEN语句 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 S PORT ( s1,s0 : IN STD_LOGIC_VECTOR ; a,b,c,d : IN STD_LOGIC ; y : OUT STD_LOGIC ) ; END ENTITY mux21 ; ARCHITECTURE one OF mux21 IS BEGIN PROCESS ( s0,s1,a,b,c,d ) BEGIN IF s1=’0’ AND s0=’0’ THEN y=a ; ELSIF s1=’0’ AND s0=’1’ THEN y=b ; ELSIF s1=’1’ AND s0=’0’ THEN y=c ; ELSIF s1=’1’ AND s0=’1’ THEN y=d ; ELSE y=NULL ; END IF ; END PROCESS ; END ARCHITECTURE one ; CASE 语句 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 IS PORT ( s1,s0 : IN STD_LOGIC_VECTOR ; a,b,c,d : IN STD_LOGIC ; y : OUT STD_LOGIC ) ; END ENTITY mux21 ; ARCHITECTURE two OF mux21 IS SIGNAL s : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; BEGIN s=s1 s0 ; PROCESS ( s ) BEGIN CASE s IS WHEN “00” = y=a ; WHEN “01” = y=b ; WHEN “10” = y=c ; WHEN “11” = y=d ; WHEN OTHERS = NULL ; END CASE ; END PROCESS ; END ARCHITECTURE two ; 3-3 程序： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY MUXK IS PORT ( s0,s1 : IN STD_LOGIC ; a1,a2,a3 : IN STD_LOGIC ; outy : OUT STD_LOGIC ) ; END ENTITY MUXK ; ARCHITECTURE double OF MUXK IS SIGNAL tmp : STD_LOGIC ; --内部连接线 BEGIN p_MUX21A_u1 : PROCESS ( u1_s, u1_a, u1_b, u1_y ) SIGNAL u1_s, u1_a, u1_b, u1_y : STD_LOGIC ; BEGIN IF u1_s=’0’ THEN u1_y= u1_a ; ELSIF u1_y= u1_b ; ELSE u1_y= NULL ; END IF ; END PROCESS p_ MUX21A_u1 ; p_ MUX21A_u2 : PROCESS ( u2_s, u2_a, u2_b, u2_y ) SIGNAL u2_s, u2_a, u2_b, u