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Defect Parameter Extraction in Backend Process Steps Using a Multilayer Checkerboard Test S.pdf

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Defect Parameter Extraction in Backend Process Steps Using a Multilayer Checkerboard Test S

Copy of: Proc. IEEE 1995 Int. Conference on Microelectronic Test Structures, Vol.8, March 1995 Defect Parameter Extraction in Backend Process Steps Using a Multilayer Checkerboard Test Structure Christopher Hess, Larg H. Weiland Institute of Computer Design and Fault Tolerance (Prof. Dr. D. Schmid) University of Karlsruhe, P. O. Box 6980, D-76128 Karlsruhe, Germany Phone: +49-721-6084217, FAX: +49-721-370455, email: hess@informatik.uni-karlsruhe.de Abstract To control defect appearance in numerous conducting layers of backend process steps, a novel multilayer checkerboard test structure (MCTS) is presented. The Separation and localization of defects - causing electrically detectable intralayer short circuits as well as interlayer short circuits - will be achieved by dividing the chip area into distinguishable small subchips inside given standard boundary pads without using any active semiconductor devices. The precise localization facilitates a versatile optical defect parameter extraction. 1 INTRODUCTION oday’s complexity of integrated circuits requires more and Tmore conducting backend layers to connect all circuit cells and devices. So, defects that cause typical backend faults inside a layer (intralayer short) and also between adjacent layers (interlayer shorts) gain more importance in defect statistics. For that, especially designed test structures to control the backend process steps for polysilicon and metal layers are in demand that combine the following partly contrasting conditions: ? Large defect sensitive area to detect random defects even if the defect density is low. ? Layer sensitive defect separation to assign electrically detected defects to a specific layer. ? Precise defect localization to simplify optical defect parameter extraction. ? No active semiconductor devices in test structures especially to control backend process steps. Generally basic geometrical layout objects like comb lines and serpentine lines are used to investigate defect appeara