4-bit bidirectional universal shift regist-DATA SHEET.pdfVIP

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4-bit bidirectional universal shift regist-DATA SHEET.pdf

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4-bit bidirectional universal shift regist-DATA SHEET

DATA SHEET Product specification File under Integrated Circuits, IC06 December 1990 INTEGRATED CIRCUITS 74HC/HCT194 4-bit bidirectional universal shift register For a complete data sheet, please also download: ? The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications ? The IC06 74HC/HCT/HCU/HCMOS Logic Package Information ? The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines December 1990 2 Philips Semiconductors Product specification 4-bit bidirectional universal shift register 74HC/HCT194 FEATURES ? Shift-left and shift-right capability ? Synchronous parallel and serial data transfer ? Easily expanded for both serial and parallel operation ? Asynchronous master reset ? Hold (“do nothing”) mode ? Output capability: standard ? ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT194 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The functional characteristics of the 74HC/HCT194 4-bit bidirectional universal shift registers are indicated in the logic diagram and function table. The registers are fully synchronous. The “194” design has special features which increase the range of application. The synchronous operation of the device is determined by the mode select inputs (S0, S1). As shown in the mode select table, data can be entered and shifted from left to right (Q0 → Q1 → Q2, etc.) or, right to left (Q3 → Q2 → Q1, etc.) or parallel data can be entered, loading all 4 bits of the register simultaneously. When both S0 and S1 are LOW, existing data is retained in a hold (“do nothing”) mode. The first and last stages provide D-type serial data inputs (DSR, DSL) to allow multistage shift right or shift left data transfers without interfering with parallel load operation. Mode select and data inputs are edge-triggered, responding only to the LOW-to-HIGH transition of the clock (CP). Therefore, the only timing restriction is that the mode control and selected data inp