compiler-friendly.pptVIP

Code Optimization IISeptember 27, 2006 Topics Machine Dependent Optimizations Understanding Processor Operations Branches and Branch Prediction Getting High Performance Don’t Do Anything Stupid Watch out for hidden algorithmic inefficiencies Write compiler-friendly code Help compiler past optimization blockers: function calls memory refs. Tune Code For Machine Exploit instruction-level parallelism Avoid unpredictable branches Make code cache friendly Covered later in course Modern CPU Design CPU Capabilities of Pentium IV Multiple Instructions Can Execute in Parallel 1 load, with address computation 1 store, with address computation 2 simple integer (one may be branch) 1 complex integer (multiply/divide) 1 FP/SSE3 unit 1 FP move (does all conversions) Some Instructions Take 1 Cycle, but Can be Pipelined Instruction Latency Cycles/Issue Load / Store 5 1 Integer Multiply 10 1 Integer/Long Divide 36/106 36/106 Single/Double FP Multiply 7 2 Single/Double FP Add 5 2 Single/Double FP Divide 32/46 32/46 Instruction Control Grabs Instruction Bytes From Memory Based on current PC + predicted targets for predicted branches Hardware dynamically guesses whether branches taken/not taken and (possibly) branch target Translates Instructions Into Operations (for CISC style CPUs) Primitive steps required to perform instruction Typical instruction requires 1–3 operations Converts Register References Into Tags Abstract identifier linking destination of one operation with sources of later operations Translating into Operations Goal: Each Operation Utilizes Single Functional Unit Requires: Load, Integer arithmetic, Store Exact form and format of operations is trade secret Operations: split up instruction into simpler pieces Devise temporary names to describe how result of one operation gets used by other operations Traditional View of Instruction Execution Imperative View Registers are fixed storage locations Individual instructions read write them Instructions must be exe