8位串行状态机.doc

1、时序控制状态机VHDL码： LIBRARY IEEE; USE IEEE.STD_logic_1164.all; ENTITY PULS8 IS PORT (RST,CLK,RU : IN STD_LOGIC:=0; SS : IN STD_LOGIC_VECTOR(2 DOWNTO 0):=000; LDO,ROUT,P,CT,COUT : OUT STD_LOGIC:=0); END ENTITY PULS8; ARCHITECTURE behav OF PULS8 IS TYPE states IS(S0,S1,S2,S3,S4,S5,S6,S7,S8); SIGNAL ST : states:=S0; BEGIN PROCESS(CLK,RST,RU,SS) BEGIN IF RST=0 THEN ST =S0; ELSIF (CLKEVENT AND CLK =1 AND RU =1) THEN CASE ST IS WHEN S0 = IF SS=000 THEN ST =S1;LDO=0;ROUT=0;COUT=0;P=0;CT=0;ELSE ST=S0;END IF; WHEN S1 = IF SS=001 THEN ST =S2;LDO=1;COUT=1;P=1;CT=1;ELSE ST=S1;COUT=0;P=0;CT=0;END IF; WHEN S2 = IF SS=010 THEN ST =S3;LDO=1;COUT=1;P=1;CT=1;ELSE ST=S2;COUT=0;P=0;CT=0;END IF; WHEN S3 = IF SS=011 THEN ST =S4;LDO=1;COUT=1;P=1;CT=1;ELSE ST=S3;COUT=0;P=0;CT=0;END IF; WHEN S4 = IF SS=100 THEN ST =S5;LDO=1;COUT=1;P=1;CT=1;ELSE ST=S4;COUT=0;P=0;CT=0;END IF; WHEN S5 = IF SS=101 THEN ST =S6;LDO=1;COUT=1;P=1;CT=1;ELSE ST=S5;COUT=0;P=0;CT=0;END IF; WHEN S6 = IF SS=110 THEN ST =S7;LDO=1;COUT=1;P=1;CT=1;ELSE ST=S6;COUT=0;P=0;CT=0;END IF; WHEN S7 = IF SS=111 THEN ST =S8;LDO=1;COUT=1;P=1;CT=1;ELSE ST=S7;COUT=0;P=0;CT=0;END IF; WHEN S8 = IF RU=1 THEN ST =S0 ; ELSE ST=S8;END IF; WHEN OTHERS= ST =S0; END CASE; IF ST=S8 THEN ROUT=1; ELSE ROUT =0; END IF; END IF; END PROCESS; END ARCHITECTURE behav; 状态机控制串并转换8数码静态显示电路的状态图如下图： 时序控制状态机原理图： 时序控制状态机仿真波形图 2 、左移寄存器VHDL码： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY SHIFTER IS PORT (CLOCK,LOAD:IN STD_LOGIC; DATA:IN STD_LOGIC_VECTOR(7 DOWNTO 0); shiftout: OUT STD_LOGIC); END SHIFTER; ARCHITECTURE ONE OF SHIFTER IS BEGIN PROCESS(CLOCK,LOAD) VARIABLE REG8: STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN IF CLOCKEVENT AND CLOCK=1 THEN IF LOAD=0 THEN REG8:=DATA; ELSE REG8(1 DOWNTO 7):=REG8(0 DOWNTO 6); REG8(0):=0; shiftout = REG8(7); END IF; END IF; END PROCESS; END ONE; 左移寄存器原理图： 左移寄存器仿真波形图： 3、7段16进制译码器VHDL码：： libra