EDA部分习题参考完整答案.docVIP

部分习题参考答案 3.6 习题3 3.合法标识符：my_counter、Decoder_1、data__BUS、Sig_N 非法标识符：2FFT、Sig_#N、Not-Ack、ALL_RST_、return、entity 7.参考程序为： entity NOR2a is Port( A,B: in std_logic; C : out std_logic ); end NOR2a; 15. Q= 4.4 习题4 1.用PROCESS语句和CASE-WHEN语句，参考程序如下： library ieee; use ieee.std_logic_1164.all; entity decoder3_8 is port(a,b,c,g1,g2a,g2b: in std_logic; y: out std_logic_vector(7 downto 0)); end decoder3_8; architecture a of decoder3_8 is signal dz:std_logic_vector(2 downto 0); begin dz=cba; process (dz,g1,g2a,g2b) begin if(g1=1and g2a=0and g2b=0)then case dz is when 000= y when 001= y when 010= y when 011= y when 100= y when 101= y when 110= y when 111= y when others=y=XXXXXXXX; end case; else y end if; end process; end ; 用WHEN-ELSE语句，参考程序如下： …… architecture a1 of decoder3_8 is signal dz:std_logic_vector(2 downto 0); begin dz=cba; doutwhen dz=000 else when dz=001 else when dz=010 else when dz=011 else when dz=100 else when dz=101 else when dz=110 else when dz=111 else XXXXXXXX; end a1; 2.参考程序如下： entity v74x148 is port ( s: in std_logic; i: in std_logic_vector ( 7 downto 0 ); y: out std_logic_vector ( 2 downto 0 ); yex , ys: out std_logic ); end v74x148; architecture behave of v74x148 is begin process ( s , i ) variable j，k: integer range 7 downto 0; variable done: bit; begin done := ‘0’; ys=’0’; if s = ‘1’ then yex= ’1’; ys = ‘1’; y = “111”; else for j in 7 downto 0 loop if done = ‘1’ then null; elsif i(j)