同步有限状态机代码.docVIP

//同步有限状态机代码 ----------------------? module?floatadder(clk,reset,ix,iy,oz,ofw);//定义模块端口;? input?clk,reset; //时钟、复位信号;?? input[31:0]ix,?iy; //输入信号;??????? output[31:0]oz; //输出信号;?? output?ofw;? //溢出位信号;? reg[31:0]oz;? reg[23:0]xm,ym,zm; //定义尾数;? reg[7:0]xe,ye,ze;? //定义阶码 reg zs; //定义输出信号符号位 reg?mc; //尾数相加溢出位 reg[2:0]?state,nextstate; //状态? parameter??start?=3b000,? zerock=3b001,? exequal=3b010,? addm?=3b011,? infifl=3b100,? zerofl=3b101,? over=3b110;? assign ofw=(state==over)?1:0;//判断溢出位 ?//每一个时钟产生一个可能的状态变化 always@(posedge clk)? if(!reset)?? state=start;? else? state=nextstate;?? //产生下一个状态的组合逻辑 always@(state)? case(state)? start:? begin? xe=ix[30:23];? xm={1b1,ix[22:0]};? ye=iy[30:23];? ym={1b1,iy[22:0]};? nextstate=?zerock;? end??? ?//操作数检查，判断操作数是否为0;? zerock:? ? ? begin? zm=ym;? ze=ye;? zs=iy[31];? oz={zs,ze,zm[23:1]};? nextstate=over;? end? else? nextstate=exequal;? end? end? //尾数求和运算;? addm:? begin? ze=xe;? if(iy[31])? {mc,zm}=xm+(~ym);? else? {mc,zm}=xm+ym;? if(zm==24b0)? nextstate=over;? else? nextstate=infifl;? end? //结果规格化操作;? infifl:? begin? if(mc)? begin? zm={mc,zm[23:1]};? ze=ze+1;? zs=ix[31];? oz={zs,ze,zm[22:0]};? if(ze==8b1111_1111)?//溢出 nextstate=over;? else? nextstate=zerofl;? if(xm==0)? begin? {ze,zm}={ye,ym};? nextstate=over;? end? else? if(ym==0)? begin? ?{ze,zm}={xe,xm};? nextstate=over;? end? else? nextstate=exequal;? end? ?//对阶操作，使阶码相等;? exequal:?? begin? if(xe==ye)? nextstate=addm;? else? if(xeye)? begin? ye=ye+1;?//阶码左移，阶码加1;? ym={1b0,ym[23:1]};? if(ym==0)? begin? zm=xm;? ze=xe;? zs=ix[31];? oz={zs,xe,zm[23:1]};? nextstate=over;? end? else? nextstate=exequal;? end? else? begin? xe=xe+1;?//阶码左移，阶码加1;? xm={1b0,xm[23:1]};? if(xm==0)? begin? end? else? nextstate=zerofl;? end? //结果做舍入处理;? zerofl:? begin? if(zm[23]==1b1)? begin? zm={1b0,zm[23:1]};//?向左移位;? ze=ze-1;? zs=ix[31];? oz={zs,ze,zm[22:0]};? nextstate=zerofl;? end? else? if(zm[23:22]==2b0)? begin? zm={zm[22:0],1b0};?//?向右移位;? ze=ze