ModuleBased Partial Reconfiguration.docVIP

Module-Based Partial Reconfiguration The Module-based Partial Reconfiguration flow is based on the Xilinx Modular Design methodology. The designer should read and understand Modular Design in Chapter 4 of this reference guide before proceeding. Defining Reconfigurable Modules Partial Reconfiguration involves defining distinct portions of an FPGA design to be reconfigured while the rest of the device remains in active operation. These portions are referred to as reconfigurable modules. Reconfigurable modules have the following properties: The reconfigurable module height is always the full height of the device The reconfigurable module width ranges from a minimum of four slices to a maximum of the full-device width in four-slice increments. Horizontal placement must always be on a four-slice boundary; the leftmost placement being x = 0, 4, 8, … All logic resources encompassed by the width of the module are considered part of the reconfigurable modules bitstream frame. This includes slices, TBUFs, block RAMs, multipliers, IOBs, and most importantly, all routing resources. Clocking logic (BUFGMUX, CLKIOBs) is always separate from the reconfigurable module. Clocks have separate bitstream frames. IOBs immediately above the top edge and below the bottom edge of a reconfigurable module are part of the specific reconfigurable modules resources. If a reconfigurable module occupies either the leftmost or rightmost slice column, all IOBs on the specific edge are part of the specific reconfigurable modules resources. To help minimize problems related to design complexity, the number of reconfigurable modules should be minimized (ideally, just a single reconfigurable module, if possible). This said, the number of slice columns divided by four is the only real limit to the number of defined reconfigurable module regions. A reconfigurable modules boundary cannot be changed. The position and region occupied by any single reconfigurable module is always fixed. Reconfigurable m