《EDA技术》习题(解答)5.docVIP

《EDA技术》习题 5 习 题 5-1 归纳利用Quartus II进行VHDL文本输入设计的流程：从文件输入一直到SignalTap II测试。P95~P115 答：1 建立工作库文件夹和编辑设计文件；2 创建工程；3 编译前设置；4 全程编译；5 时序仿真；6 引脚锁定；7 配置文件下载；8 打开SignalTap II编辑窗口；9 调入SignalTap II的待测信号；10 SignalTap II参数设置；11 SignalTap II参数设置文件存盘；12 带有SignalTap II测试信息的编译下载；13 启动SignalTap II进行采样与分析；14 SignalTap II的其他设置和控制方法。 5-2 由图5-40和图5-41，详细说明工程设计CNT10的硬件工作情况。P114~P115 答：图5-40给出工程设计CNT10的十进制计数工作情况；当计数CQ或CQI到9时,计数进位COUT输出正脉冲。图5-41给出工程设计CNT10的十进制计数和内部计数节点CQI计数线性递增的信号波形的工作情况。 5-3 如何为设计中的SignalTap II加入独立采样时钟?试给出完整的程序和对它的实测结果。P115 答：为SignalTap II提供独立时钟的方法是在顶层文件的实体中增加一个时钟输入端口，如语句:LOGC_CLK:IN STD_LOGIC;在此实体中不必对其功能和连接具体定义，而在SignalTap II的参数设置中则可以选择LOGC_CLK为采样时钟。 5-4 参考QuartusII的Help，详细说明Assignments菜单中Settings对话框的功能。 (1)说明其中的Timing RequirementsQptions的功能、他用方法和检测途经。 Specifying Timing Requirements and Options (Classic Timing Analyzer) You can specify timing requirements for Classic timing analysis that help you achieve the desired speed performance and other timing characteristics for the entire project, for specific design entities, or for individual clocks, nodes, and pins. When you specify either project-wide or individual timing requirements, the Fitter optimizes the placement of logic in the device in order to meet your timing goals. You can use the Timing wizard or the Timing Analysis Settings command to easily specify all project-wide timing requirements, or you can use the Assignment Editor to assign individual clock or I/O timing requirements to specific entities, nodes, and pins, or to all valid nodes included in a wildcard or assignment group assignment. To specify project-wide timing requirements: On the Assignments menu, click Settings. In the Category list, select Timing Analysis Settings. To specify project-wide tSU, tH, tCO, and/or tPD timing requirements, specify values under Delay requirements. To specify project-wide minimum delay requirements, specify options under Minimum delay requirements. Under Clock Settings, select Default require