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Rutgers University CS 416: Operating Systems CC-NUMA Multiprocessors CPU Memory memory bus I/O bus disk cache network Non-uniform access to different memories Hardware allows remote memory accesses and maintains cache coherence Scalable interconnect ? more scalable than bus-based UMA systems Also naturally supports single-image operating systems Complex hardware coherence protocols Mem Cntrl CPU Memory memory bus I/O bus disk cache Mem Cntrl Rutgers University CS 416: Operating Systems Multicomputers Network of computers: “share-nothing” -- cheap Distributed resources: difficult to program Message passing Distributed file system Challenge: build efficient global abstraction in software CPU Memory memory bus I/O bus disk Net interface cache CPU Memory memory bus I/O bus disk Net interface cache network Rutgers University CS 416: Operating Systems Next Time Processes * * * * * * Rutgers University CS 416: Operating Systems Fetch-decode-execute with Traps Fetch: if ((PC 100) (mode register == USR)) then memory exception Decode: if (instruction is a trap) then set the PC = PC set the PC = 68 set the mode = SYS goto fetch if ((destination register == mode) (mode register == USR)) then mode exception Execute: … Rutgers University CS 416: Operating Systems How does the OS know which service the user program wants to invoke on a trap? User program passes to the OS a number that encodes which OS service is desired This example machine could include the trap ID in the instruction itself: Most real CPUs have a convention for passing the trap ID in a set of registers E.g. the user program sets register 0 with the trap ID, then executes the trap instruction Traps Trap opcode Trap service ID Rutgers University CS 416: Operating Systems Returning from a Trap How to get back to user mode and the users code after a trap? Could we use two instructions? Set the mode register = 1 then set the PC? But after the mode bit is set