一种新型两道时间交织高阶ΣΔ调制器电路_2008.docVIP

一种新型两通道时间交织高阶ΣΔ调制器 杨骁，陈贵灿 （西安交通大学电子与信息工程学院，陕西 西安，710049） 摘要: 为了减小两通道时间交织ΣΔ调制器中系数失配引起的折叠噪声以及降低调制器实现电路复杂程度，提出了一种新的两通道时间交织高阶ΣΔ调制器。在传统调制器的噪声传递函数(NTF)中增加一个z=－1的零点，减小了NTF在高频处的幅值，从而减小了折叠到信号带宽内的噪声。以一个传统单通道单环4阶4位前馈分布型ΣΔ调制器结构为原型，运用块数字滤波器基本原理以及时域等效的方法，得到了其两通道时间交织结构的实现电路。该调制器电路前三级的两个通道能够共享运算放大器，减小了有源元器件的数目。对包含了系数失配的调制器进行了建模和仿真，仿真结果表明，该两通道时间交织高阶调制器能够有效地抑制折叠噪声，提高了调制器的性能。 关键词：ΣΔ调制器；折叠噪声；时间交织；块数字滤波器； 中图分类号: TN432 文献标识码：A A Novel Two-Channel Time-Interleaved High-order ΣΔ Modulator YANG Xiao, CHEN Gui-can (School of Electronics and Information, Xi’an Jiaotong University, Xi’an 710049, China) Abstract: To alleviate the folded noise caused by coefficient mismatches between the two channels of two-channel time-interleaved (TI) ΣΔ modulators and simplify the circuit of the modulators, a novel two-channel time-interleaved high-order ΣΔ modulator is proposed. Adding a zero at z=-1 to a conventional noise transfers function (NTF), the amplitude of the NTF at high frequency can be reduced, and then the amount of the folded noise is reduced. Based on the theory of block digital filter and the method of timing equivalent, the circuit of implementation for the proposed modulator is derived from the prototype of a conventional single-channel single-loop fourth-order 4-bit distributed feedforward ΣΔ modulator, in which the opamps can be shared by tow channels of the first three stages, resulting in a simplification in hardware complexity. A system model containing coefficient mismatches is built and simulated. Simulation results show that the proposed two-channel TI high-order ΣΔ modulator can alleviate the folded noise and improve the performance. Keywords: ΣΔ modulator; folded noise; time-interleaved; block digital filter 近代通信系统对高精度、宽带数模转换器的需求推动了对高精度宽带ΣΔ模数转换器(ADC)的研究。为了增大调制器的带宽，一种最直接的方法是提高采样频率。但是，现有的CMOS集成电路工艺水平限制了运算放大器的高频性能，使得基于开关电容电路的高速ΣΔ ADC的设计很困难[1]。时间交织技术是一种提高ADC转换速率的有效方法，它采用多个并行工作的低速ADC来实现高速转换率[2,3]。时间交织技术已经成功地运用在ΣΔ调制器中，但是，在电路实现时存在两个缺点：由于模拟电路的非理想特性，各个通道之间存在失配，会产生信号频谱的混叠，严重影响了调制器的性