Lecture3 Verilog程序设计方法 - v2.0.ppt

More on Blocking Called blocking because…. The evaluation of subsequent statements RHS are blocked, until the LHS assignment of the current statement is completed. d clk q1 q2 q3 Lets code this module pipe(clk, d, q); input clk,d; output q; reg q; always @(posedge clk) begin q1 = d; q2 = q1; q3 = q2; end endmodule Simulate this in your head… Remember blocking behavior of: LHS assigned before RHS of next evaluated. Does this work as intended? Slide taken direct from Eric Hoffman * More on Non-Blocking Lets try that again d clk q1 q2 q3 Lets code this module pipe(clk, d, q); input clk,d; output q; reg q; always @(posedge clk) begin q1 = d; q2 = q1; q3 = q2; End endmodule; With non-blocking statements the RHS of subsequent statements are not blocked. They are all evaluated simultaneously. The assignment to the LHS is then scheduled to occur. This will work as intended. Slide taken direct from Eric Hoffman * So Blocking is no good and we should always use Non-Blocking?? Consider combinational logic module ao4(z,a,b,c,d); input a,b,c,d; output z; reg z,tmp1,tmp2; always @(a,b,c,d) begin tmp1 = a b; tmp2 = c d; z = tmp1 | tmp2; end endmodule Does this work? The inputs (a,b,c,d) in the sensitivity list change, and the always block is evaluated. New assignments are scheduled for tmp1 tmp2 variables. A new assignment is scheduled for z using the previous tmp1 tmp2 values. Slide taken direct from Eric Hoffman * Why not non-Blocking for Combinational Can we make this example work? What is the downside of this? module ao4(z,a,b,c,d); input a,b,c,d; output z; reg z,tmp1,tmp2; always @(a,b,c,d) begin tmp1 = a b; tmp2 = c d; z = tmp1 | tmp2; end endmodule Yes Put tmp1 tmp2 in the trigger list module ao4(z,a,b,c,d); input a,b,c,d; output z; reg z,tmp1,tmp2; always @(a,b,c,d,tmp1,tmp2) begin tmp1 = a b; tmp2 = c d; z = tmp1 | tmp2; end endmodule Slide taken direct from Eric Hoffman * 任务（task） 函数（function） 任务和函数结构之间的