power device.ppt

Summary : ? Power devices : application fields ? Power MOS : structure and technology ? Technological Road-map HV and LV devices Passivation Nitride deposition (10K?) Nitride photolithography (mask, etch) Resist removal Back finishing process steps Lamination (cover the front with TAPE) Lapping Back etch (chemical – SEZ) Back metallization (Ti-Ni-Au) 29 30 G D S CGD 7 7 CGS Drain-source capacitor (CDS) G D S 1 2 4 6 5 7 7 2 1 5 6 4 3 3 Parasitic capacitors 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 10 9 11 10 12 11 13 13 14 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 D C Rp S Parasitic structure :Turn-on conditions i · Rp 3 Vbe Static condition dt dV i = C dt dV ≥ Rp · C Vbe Dynamic condition POWER MOS CURRENT CAPABILITY G S D + + - 0 VGS VTH VDS 0 ID = 0 G S D + + - VGS ~ VTH VDS 0 VGS VTH VDS 0 ID 0 G S D + + - VDS [V] ID [A] RON VG Drain current : ID Output Resistance:RON PMOS: output characteristics 10 20 30 10 20 30 0 40 0 Drain current Vs Gate voltage 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 IDS [A] VDS [V] VDS [V] IDS [A] Drain current Vs Temperature ?T ?ID = f ( , ) ?T ?VT ?T ?m 120 T=25 oC T=125 oC 5 0 10 15 0 40 80 The PMOS structure has parasitic bipolar element inside. The conduction of the drain current happens for majority charges with vertical flux. The current capability depends on geometrical parameter (WC) and phisics ones (Xox , LC , VT ) If the temperature increases, the output resistance increases also. Power MOS : OUTPUT resistance analysis (RDSon) D S G D G S N- P+ N+ The resistence due to parasitic j-fet Repy Rc Racc Rjf Rsource mtl Rback mtl RDSon = Rch + Racc + Rjf + Repy + Rfront mtl + Rback mtl Repy Repy Repy = rN XN A - k - Lc d Rc mQN 1 WC LC Rc = = mCox(VG-VT) 1 WC LC Channel resistance Lc Lc Channel lenght Wc Channel perimeter Rc = meox (VG-VT) 1 WC LCXox Channel resistance Lc d Rc Racc = meox (VG-VT) k 2 WC d Xox Accumulation resistance Lc d Racc d d = distance between 2