lec_Gate_Sizing课件.pptVIP

ELEC 7770: Advanced VLSI Design (Agrawal) ELEC 7770: Advanced VLSI Design (Agrawal) Spring 2010, Mar 10 ELEC 7770: Advanced VLSI Design (Agrawal) * ELEC 7770Advanced VLSI DesignSpring 2010Gate Sizing Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@ /~vagrawal/COURSE/E7770_Spr10 Clock Distribution clock Spring 2010, Mar 10 * ELEC 7770: Advanced VLSI Design (Agrawal) Clock Power Pclk = CLVDD2f + CLVDD2f / λ + CLVDD2f / λ2 + . . . stages – 1 1 = CLVDD2f Σ ─ n= 0 λn where CL = total load capacitance λ = constant fanout at each stage in distribution network Clock consumes about 40% of total processor power. Spring 2010, Mar 10 * ELEC 7770: Advanced VLSI Design (Agrawal) Delay of a CMOS Gate CMOS gate CL Cg Cint Propagation delay through the gate: tp = 0.69 Req(Cint + CL) ≈ 0.69 ReqCg(1 + CL /Cg) = tp0(1 + CL /Cg) Gate capacitance Intrinsic capacitance Spring 2010, Mar 10 * ELEC 7770: Advanced VLSI Design (Agrawal) Req, Cg, Cint, and Width Sizing Req: equivalent resistance of “on” transistor, proportional to L/W; scales as 1/S, S = sizing factor Cg: gate capacitance, proportional to CoxWL; scales as S Cint: intrinsic output capacitance ≈ Cg, for submicron processes tp0: intrinsic delay = 0.69ReqCg; independent of sizing Spring 2010, Mar 10 * ELEC 7770: Advanced VLSI Design (Agrawal) Effective Fan-out, f Effective fan-out is defined as the ratio between the external load capacitance and the input capacitance: f = CL/Cg tp = tp0(1 + f ) Spring 2010, Mar 10 * ELEC 7770: Advanced VLSI Design (Agrawal) Sizing an Inverter Chain Cg1 Cg2 CL 1 2 N Cg2 = f2Cg1 tp1 = tp0 (1 + Cg2/Cg1) tp2 = tp0 (1 + Cg3/Cg2) N N tp = Σ tpj = tp0 Σ (1 + Cgj+1/Cgj) j=1 j=1 Spring 2010, Mar 10 * ELEC 7770: Advanced VLSI Design (Agrawal) Minimum Delay Sizing Equate partial derivatives of tp with respect to Cgj to 0: 1/Cg1 – Cg3/Cg22 = 0, etc. or Cg22 = Cg1×Cg3, etc. i.e., gate capacitance