《512K x 72 Synchronous Pipeline》.pdfVIP

WEDPZ512K72V-XBX 512K x 72 Synchronous Pipeline Burst ZBL SRAM FEATURES DESCRIPTION  Fast clock speed: 150, 133, and 100MHz The WEDC SyncBurst - SRAM employs high-speed, low-power  Fast access times: 3.8ns, 4.2ns, and 5.0ns CMOS design that is fabricated using an advanced CMOS process. WEDC’s 32Mb SyncBurst SRAMs integrate two 512K x 36  Fast OE# access times: 3.8ns, 4.2ns, and 5.0ns SSRAMs into a single BGA package to provide 512K x 72  High performance 3-1-1-1 access rate configuration. All synchronous inputs pass through registers 3.3V ± 5% power supply controlled by a positive-edge-triggered single-clock input (CLK). The ZBL or Zero Bus Latency Memory utilizes all the bandwidth  I/O supply voltage 3.3V or 2.5V in any combination of operating cycles. Address, data inputs, and Common data inputs and data outputs all control signals except output enable and linear burst order are Byte write enable and global write control synchronized to input clock. Burst order control must be tied “High or Low.” Asynchronous inputs include the sleep mode enable (ZZ). Six