Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits.pdfVIP

Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits Bipul C Paul, Cassondra Neau, and Kaushik Roy School of Electrical and Computer Engineering, Purdue University West Lafayette, IN 47907-1285, USA E-mail: {paulb, crotty, kaushik}@ Tel: 1-765-494 0759, Fax: 1-765-494 3371 Abstract— A Body biasing technique has recently been pro- fault testing of a circuit a set of critical paths are constructed posed for microprocessors in sub-100 nm technology generations by selecting longest paths based on the static timing analysis [10], [11]. It is shown that forward body bias (FBB) reduces the [3], [4]. Timing analysis estimates the earliest, latest and the leakage power and suppresses the effect of process variation while reducing the complexity of dual Vth technology. In this paper, we average signal arrival times for each pin-to-pin pair of all the study the effect of body bias on the delay fault testing of CMOS gates in the circuit. Based on the estimation, the path delays, circuits. We analyze the impact of both fixed and adaptive body which are the accumulated delays of each gates in the path, biasing techniques on test cost and the quality of test. Statistical are calculated. However, due to process variation, the arrival analysis on several benchmark circuits shows that the adaptive times of the gates are expected to vary significantly. Hence, body biasing design will have the most effective impact on delay fault by maintaining the test cost at its minimum under proc