一种低功耗高稳定性晶体振荡器芯片的设计.pdfVIP

27 12 Vol. 27 No . 12 2010 12 MICROELECTRONICS COMPU TER December 2010 陈红梅, 徐静平, 钟德刚 ( , 430074) : 分析了传统Pierce 振荡器不足, 提出了改进型的振荡器结构, 并基于0. 3 m CMOS 工 , 设计实现了 一 款低功耗高稳定性的晶体振荡器芯片. 芯片有两种工作模式: 正常工作模式和低功耗模式. 测试结果表明, 在电源 电压为 V振荡频率为30 MH z负载电容1 pF 时, 芯片消耗总电流低于 mA, 振荡电路消耗电流仅为0. 6 m A, 输出占空比为 0 0. 8% 的方波信号, 其频率随电源电压的变化率仅为0. 10- 6 . 引入低功耗模式, 振荡器消耗 电流降低至3 A 以下, 和传统结构相比, 功耗降低了60% , 频率随电压稳定性提高了10 倍. : Pierce 晶体振荡器; 低功耗; 高稳定性; CMOS 工 : T N432 : A : 1000- 7180( 2010) 12- 010 - 04 Design of Crystal Oscillator Chip with Low Power and High Stability CHEN H ongmei, XU Jingping, ZH ON G Degang ( Department of Electronics Science and Technology, H uazhong University of Science and T echnology, Wuhan 430074, China) Abstract: A crystal oscillat or chip w ith low pow er and high stability is presented. On t he basis of analyzing the disadvant ages of the conventional Pierce crystal oscillator, a novel crystal oscillator structure has been proposed. The chip can work under two modes: normal operating mode and pow erdissipat ion mode. Based on 0. 3 m CMOS process, the test results show that total consumpt ion of the chip is less than mA with pow er supply voltage of V, oscillation frequency of 30 MH z, load capacitance of 1 pF, and t he oscillator circuit is only 0. 6 mA, out put square w ave signal with dut y cycle of 0 0. 8% , frequency stabili t y 0. 10- 6 . By introducing t he powerdissipation mode, current consumption of t he oscillation circuit is dropped to 3 A. Compared w ith the conventional structure, the powerdissipation has been reduced 60% , f requency st abilit y raised ten times. Key words: Pierce crystal oscillator; low powerdissipation; highstability ; CMOS t echnology