VLSI波形发生器课程设计.doc

波形发生器的设计 一、波形发生器是一种常用的信号源，广泛地应用于电子电路、自动控制系统和教学实验等领域。、、、library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity sin is port(clk:in std_logic; en:in std_logic; fchu:in std_logic_vector(2 downto 0); --fchu输出频率选择 pword:in std_logic_vector( 7 downto 0);--相位调节0~255 z1,z2,z3,z4:out std_logic; addr_rom:buffer std_logic_vector(7 downto 0);--addr_rom地址采点，从LCP_ROM相应的地址读取数据 xtime:in std_logic_vector(1 downto 0) --时间触发选择，从那个LCP_ROM中调取波形，其选择的波开跟DA输出通道是相一致的。 ); end sin ; architecture a of sin is signal s:std_logic_vector(2 downto 0); signal temp: integer range 0 to 715827880; signal address: std_logic_vector(7 downto 0); signal fre_count: std_logic_vector(31 downto 0); signal fw: std_logic_vector(31 downto 0); signal pw: std_logic_vector(7 downto 0); signal xx:std_logic_vector(1 downto 0); signal cda:std_logic_vector(1 downto 0); signal fo:std_logic_vector(31 downto 0); begin s=fchu; xx=xtime; process(clk,s) begin if clkevent and clk=1 then case s is when 001= temp when 010= temp=143165576; when 011= temp=214748364; when 100= temp=286331152; when 101= temp=357913940; when 110= temp=429496728; when 111= temp=715827880; when others= temp end case; end if; fo=conv_std_logic_vector(temp,32); end process; process(clk,fo,en,pword) begin fw=fo; if clkevent and clk=1 then if en=1 then fre_count=fre_count+fw; end if; end if; end process; process(clk,pw) begin pw=pword; if clkevent and clk=1 then if en=1 then address=fre_count(31 downto 24)+pw; end if; end if; addr_rom=address; end process; process(xx,clk) begin if xx=00 then z1=clk; else z1=1; end if; if xx=01 then z2=clk; else z2=1; end if; if xx=10 then z3=clk; else z3=1; end if; if xx=11 then z4=clk; else z4=1; end if; end process; end a; （2）调频调相模块电路图 幅度调节与波形通道输出模块 library ieee;