基于RISC架构的MIPS指令兼容处理器cpu设计.docVIP

摘 要 基于RISC架构的MIPS指令兼容处理器是通用高性能处理器的一种。其架构简洁，运行效率高，在高性能计算，嵌入式处理，多媒体应用等各个领域得到了广泛应用。基于FPGA的CPU IP核设计具有易于调试，便于集成的特点。在片上系统设计方法日趋流行的趋势下，掌握一套复杂的CPU设计技术十分必要。 本设计实现了一个具有标准的32位5级流水线架构的MIPS指令兼容CPU系统。具备常用的五十余条指令，解决了大部分数据相关，结构相关，乘除法的流水化处理等问题，并实现了可屏蔽的中断网络。另外配有专用的汇编集成开发环境，可以做到汇编级程序开发。由于此设计可直接应用于FPGA芯片中，因此具有很高的实用价值。本设计体系简洁，易于扩展，非常适合以IP核的形式作为嵌入式设备的高性能单片机或MCU使用。同时，其设计过程是一个最小系统扩展法的实现范例，论文阐述了如何将一个设计雏形发展成实用化的成品的过程。 在文章编排上，本文首先讲述了RISC思想的由来、MIPS处理器的特点及其指令集、MIPS处理器的三种基础结构，随后以最小系统扩展法为线索介绍了CPU的若干理论问题及本设计的解决方法，之后阐述了CPU的顶层结构和模块接口。最后的仿真验证表明了此方案可以在Altera系列FPGA芯片中稳定正确的运行。 关键词: RISC; MIPS; 32位处理器; 流水线; 中断 Abstract RISC architecture based MIPS instruction compatible processor is one kind of general high performance processors. Considering its simplicity of architecture and high efficiency of computing, it is widely used in many fields such as high capability ofcomputing, embedded solutions, and multimedia applications. The CPU IP core design based on FPGA has many advantages such as easy to debug and convenient to integrate. It is necessary to maintain a complex CPU designing technique with the fashionable trend of SOC design methods. This paper discusses a MIPS instruction compatible processor under the 32-bit 5-level-pipeline architecture. It implemented more than fifty frequently used instructions, solved most of data relationships, architecture relationships and the problems of pipeline adopt of multiply/division, and implemented an interrupt system that can be shielded. In addition, an assembly language development environment is implemented which is appropriate to this design, so it can achieve an assemble-level development. Because the design can be deployed to an FPGA chip, it has a considerable practicability. The architecture of this design is concise and easy to extend, so it is very suitable to use as an SCM or MCU in embedded devices in the form of IP core. Moreover, the course of the design is a typical example of minimum-system dilatation. This paper expatiate how to build a prac